The present invention generally relates to semiconductor devices, such as a CCD solid-state image sensing device, in which various types of voltages such as a ground voltage, a positive voltage, and a negative voltage are applied to each of a plurality of terminals, and more particularly, to protective circuits to be connected with terminals of such a semiconductor device.
As an example of the semiconductor device, a CCD solid-state image sensing device is schematically shown in FIG. 5. A plurality of light receiving portions 1 are arranged in a matrix form, and vertical transfer registers 2 are provided adjacently to the light-receiving portions 1 of each column. A horizontal transfer register 3 is provided at an end of each vertical transfer register 2. An output circuit 4 is connected with one end of the horizontal transfer register 3.
An electric charge of a signal photoelectrically converted at each light-receiving portion 1 is read at the vertical transfer register 2, and then transferred to the horizontal transfer register 3 through the vertical transfer register 2. The output circuit 4 converts the signal electric charge transferred thereto through the horizontal transfer register 3 into a voltage for each pixel and outputs the voltage. The vertical transfer registers 2 are four-phase driven. A ternary pulse changing from a positive voltage to a negative voltage, (the ternary pulse assumes, for example, -9 V, 0 V, and 15 V) is applied to terminals .phi.V1 and .phi.V3 of the vertical transfer register to allow the vertical transfer register 2 to read the signal electric charge from the corresponding light receiving portions 1. A negative voltage binary pulse assuming, for example, -9 V and 0 V is applied to terminals .phi.V2 and .phi.V4 of the vertical transfer register 2 not to allow the vertical transfer register 2 to read the signal electric charge. The horizontal transfer register 3 is two-phase driven. A positive voltage binary pulse assuming, for example, 0 V and 5 V is applied to terminals .phi.H1 and .phi.H2.
As described above, the CCD solid-state image sensing device is supplied with various types of voltages including the ground voltage (GND), positive voltages such as a supply voltage and a positive voltage to be applied to the horizontal transfer register 3, and a negative voltage to be applied to the vertical transfer registers 2.
Each of the terminals through which the voltages are applied to elements of the device is connected with a protective circuit for protecting the interior of each element of the device. For example, because a substantially greatest electric voltage is applied to vertical transfer gates of the vertical transfer register 2 through the terminals .phi.V1 and .phi.V3, an insulation film (gate insulation film) positioned under the vertical transfer gate electrode is easily destroyed by static electricity. Therefore, a protective circuit is connected with each of the terminals of the horizontal transfer register 3 and the vertical transfer register 2 to prevent the gate insulation film for the electric charge transfer electrode from being destroyed by the static electricity. A protective circuit is also connected with each of a power supply terminal, an output terminal, and a reset drain terminal to prevent junctions in internal elements (e.g. an output MOS transistor and a reset transistor) from being destroyed. The protective circuits are constituted of MOS transistors, bipolar transistors or diodes.
An example of a protective circuit provided in a conventional CCD solid-state imaging device is shown in FIGS. 6A and 6B which are a schematic sectional view and an equivalent circuit diagram of the device, respectively. In FIGS. 6A and 6B, a vertical transfer register and a horizontal transfer register are denoted by the same reference numbers, 2 and 3, as those used in FIG. 5. Also, in these figures, reference symbol T1 denotes a terminal of the vertical transfer register 2, reference symbol C1 denotes a gate of the vertical transfer register 2, reference symbol T2 denotes a terminal of the horizontal. transfer register 3, and reference symbol C2 denotes a gate of the horizontal transfer register 3. It should be understood that the terminal T1 corresponds to the terminal .phi.V1, .phi.V2, .phi.V3, or .phi.V4 shown in FIG. 5, and that the terminal T2 corresponds to the terminal .phi.H1 or .phi.H2. In operation, the terminal T1 is supplied with either a ternary pulse ranging from a negative voltage to a positive voltage, such as, for example, -9 V, 0 V, and 15 V, or a negative voltage binary pulse (a transfer clock pulse) which assumes -9 V and 0 V. On the other hand, the terminal T2 is supplied with a positive voltage binary pulse (a transfer clock pulse) of, for example, 0 V and 5 V. The gates C1 and C2 are formed on a P-type well 6 to which the ground voltage is applied, so that an image sensing part 5 transfers an electric charge.
Reference symbols H11 and H12 denote protective circuits connected with the terminals T1 and T2, respectively, to protect the gates C1 and C2 and insulation films confronting the gates C1 and C2. Each of the protective circuits H11 and H12 is composed of a MOS transistor. The protection transistor H11 is constructed of a source 8 and a drain 10 both formed in a P-type well 7 formed on an N-type substrate 15, and a gate 9 that is formed over a channel provided between the source 8 and the drain 10 with a gate insulation film interposed between the gate 9 and the channel. Similarly, the protection transistor H12 is constructed of a source 11 and a drain 13 both formed in a P-type well 6 formed on the N-type substrate 15, and a gate 12 that is formed over a channel provided between the source 11 and the drain 13 with a gate insulation film interposed between the gate 12 and the channel. Because the terminal T1 is driven by a negative voltage, the protective MOS transistor H11 is required to be formed on the P-type well 7 to which a negative voltage (VL=-9 V) is applied. The source 8 and the gate 9 of the protective MOS transistor H11 are connected with a negative potential well terminal VL (=-9 V), and the drain 10 is connected with the terminal T1. On the other hand, the terminal T2 is driven by a positive voltage. Therefore, the protective MOS transistor H12 is required to be formed on the P-type well 6 in which the image sensing part 5 is formed and to which the ground voltage is applied. The source 11 and the gate 12 of the protective MOS transistor H12 are connected with the ground, and the drain 13 is connected with the terminal T2. A protective circuit is provided for other terminals to which a positive voltage is applied, for example, a supply terminal, an output terminal, and a reset drain terminal.
The operation of the protective MOS transistors H12 and H11 will be described below.
When static electricity that is positive with respect to the ground terminal G1 is applied to the terminal T2 for some reason, the positive static electricity is discharged (Ip1) from the terminal T2 to the ground terminal G1 owing to snapback phenomenon (described later) in the protective MOS transistor H12. Therefore, it is possible to prevent a voltage higher than a gate withstand voltage, or gate electrical strength, of the gate C2 of the horizontal transfer register 3 from being applied to the terminal T2 and prevent the insulation film 14 of the gate C2 of the horizontal transfer register 3 from being destroyed. FIG. 7 shows voltage-current characteristics of the snapback phenomenon.
When positive static electricity is applied to the terminal T2, namely, to the drain 13 of the protective MOS transistor H12, breakdown occurs between the drain 13 and the P-type well 6 (breakdown voltage VB). With the increase of the breakdown electric current (Ip2) between the drain 13 and the P-type well 6, the electric potential of the P-type well 6 rises (or becomes deep), and the protective MOS transistor H12 is turned on (snapback voltage VS). As a result, a large amount of current Ip1 flows between the drain 13 and the source 11, and the drain. voltage drops, i.e., the voltage of the terminal T2 drops.
When static electricity that is negative with respect to the ground terminal G1 is applied to the terminal T2, junction between the drain 13 of the protective MOS transistor H12 and the P-type well 6 is biased forward, and the negative static electricity is discharged (Im1) from the terminal T2 to the ground terminal G1. Thus, it is possible to prevent the insulation film 14 of the gate C2 of the horizontal transfer register 3 from being destroyed.
On the other hand, when static electricity that is positive with respect to the ground terminal G1 is applied to the terminal T1 for some reason, breakdown occurs between the drain 10 of the protective MOS transistor H11 and the P-type well 7, the electric potential of the P-type well 7 rises (or becomes deep), and the positive static electricity is discharged (Ip3) to the N-type substrate 15. Thus, it is possible to prevent the insulation film 16 of the gate C1 of the vertical transfer register 2 from being destroyed.
When static electricity that is negative with respect to the ground terminal G1 is applied to the terminal T1, junction between the drain 10 of the protective MOS transistor H11 and the P-type well 7 is biased forward, and the electric potential of the P-type well 7 drops (or becomes shallow). As a result, breakdown occurs between the P-type well 7 and the N-type substrate 15. Thus, the negative static electricity is discharged (Im2) from the terminal T1 to the ground terminal G1 through the N-type substrate 15. Thus, the insulation film 16 of the gate C1 of the vertical transfer register 2 is prevented from being destroyed.
Furthermore, when static electricity that is positive with respect to the terminal T1 is applied to the terminal T2, breakdown occurs between the drain 13 of the protective MOS transistor H12 and the P-type well 6, and the positive static electricity is discharged (Ip4) to the N-type substrate 15. Thus, the insulation film 17 positioned between the gate C1 of the vertical transfer register 2 and the gate C2 of the horizontal transfer register 3 is prevented from being destroyed.
When static electricity that is negative with respect to the terminal T1 is applied to the terminal T2, there occurs forward bias between the drain 13 of the protective MOS transistor H12 and the P-type well 6, and the electric potential of the P-type well 6 drops (or becomes shallow). As a result, breakdown occurs between the P-type well 6 and the N-type substrate 15. Thus, the negative static electricity is discharged (Im3) from the terminal T2 to the terminal T1 through the N-type substrate 15. Thus, it is possible to prevent the destruction of the insulation film 17 positioned between the gate C1 of the vertical transfer register 2 and the gate C2 of the horizontal transfer register 3.
When the static electricity is applied to the terminal T1 with respect to the terminal T2, an operation similar to the above is performed.
Japanese Patent Laid-Open Publication No. 8-116027 also discloses protective circuits for each terminal. The protective circuits are constructed of bipolar transistors wherein emitters are connected with corresponding terminals, bases are commonly connected, and collectors are connected with an N-type substrate.
Meanwhile, because the vertical transfer register of the CCD solid-state image sensing device needs to be driven with a negative voltage, protective circuits therefor should be formed on the P-type well to which a negative voltage is applied. On the other hand, to transfer an electric charge, the gates of the vertical transfer register are positioned above the P-type well to which the ground voltage is applied, similar to the image-sensing part 5. In the construction of the conventional protective circuit shown in FIGS. 6A and 6B, when static electricity is applied to the terminal T1 of the vertical transfer register 2 with respect to the ground terminal G1, the static electricity is discharged to a path leading to the N-type substrate 15 or to a path passing through the N-type substrate 15. They are the only discharge paths. The N-type substrate 15 has a comparatively high resistance (R1, R2). Thus, the time constant in discharge is comparatively great and a voltage higher than the gate electrical strength is easily applied to the gate C1 of the vertical transfer register 2, which causes destruction of the insulation film 16. That is, disadvantageously, electrostatic strength, or resistance to static electricity, is low. When the static electricity is applied between the terminals T1 and T2, the static electricity is discharged via a path leading to the N-type substrate 15 or a path through the N-type substrate 15. Thus, a disadvantage similar to the above also occurs in this case.
In the construction disclosed in Japanese Laid-Open Patent Publication No. 8-116027, all discharge paths of static electricity pass the N-type substrate. Thus, this construction has a disadvantage similar to the above.
Meanwhile, because a greatest operating voltage is applied to the terminals of the vertical transfer register, especially, terminals .phi.V1 and .phi.V3, an operating voltage of the protective circuit connected with each terminal is set to a voltage higher than that of the terminals .phi.V1 and .phi.V3. In the prior art, an operating voltage same as that for the protective circuit connected with the terminal .phi.V1, .phi.V3 is used also for the protective circuits connected with the terminals .phi.V2 and .phi.V4 of the vertical transfer register 2 and the terminals .phi.H1 and .phi.H2 of the horizontal transfer register 3 to which comparatively low operating voltages are applied. That is, although the operating voltage for such a terminal is low, the operating voltage of the protective circuit connected therewith is set high. Thus, the margin between the operating voltage of the protective circuit and a voltage destroying the gate insulation film is small, and hence, the electrostatic strength is low.